1. Technical Field of the Invention
The present invention relates to a sequential comparison-type analog-to-digital converter.
2. Related Art
As an analog-to-digital converter (ADC) mounted on a microcomputer or system LSI, a sequential comparison type is used in many cases from the viewpoint of downsizing and maintaining high precision.
FIG. 1 is a block diagram showing a configuration example of a conventional sequential comparison-type ADC. FIG. 2 is a diagram explaining a conversion operation in the sequential comparison-type ADC.
As shown in FIG. 1, the conventional sequential comparison-type ADC comprises a comparator 12, a sequential comparison control circuit 13, and a DA converter (digital-to-analog converter) 14. An input analog signal SA is held temporarily by, for example, a sample-holding circuit 11 and input to the comparator 12 as an input signal Vin.
It is assumed that the sequential comparison-type ADC has an n-bit (here, 8-bit) resolution and a full-scale voltage is VFS as shown in FIG. 2. In a first step, the sequential comparison control circuit 13 outputs a digital signal whose bit value of a first bit (b1) is “1” and whose bit values of second and subsequent bits (b2 to bn) are “0” and the DA converter 14 generates and outputs a reference analog signal Vref of a voltage corresponding to the digital signal. The voltage of the reference analog signal Vref in the first step is VFS/2. The comparator 12 compares the voltage of the input signal Vin with the voltage of the reference analog signal Vref and outputs a comparison result. The sequential comparison control circuit 13 decides the bit value of the first bit (b1) based on the comparison result. For example, when Vin is larger than Vref, b1 is decided to be “1” and when Vin is smaller than Vref, b1 is decided to be “0”. In FIG. 2, b1 is “1”. In the following explanation, “the comparator compares” means “the comparator compares voltages” and “the DA converter generates a reference analog signal corresponding to a digital signal” means “the DA converter generates a reference analog signal of a voltage corresponding to a digital signal”.
In a second step, the sequential comparison control circuit 13 outputs a digital signal whose b1 is the value (here, “1”) decided in the first step, whose bit value of the second bit (b2) is “1”, and whose bit values of third and subsequent bits (b3 to bn) are “0” and the DA converter 14 generates and outputs the reference analog signal Vref corresponding to the digital signal. In the example in FIG. 2, the reference analog signal Vref in the second step is 3VFS/4. The comparator 12 compares the input signal Vin with the reference analog signal Vref and outputs a comparison result. The sequential comparison control circuit 13 decides the bit value of the second bit (b2) based on the comparison result. For example, when Vin is larger than Vref, b2 is decided to be “1” and when Vin is smaller than Vref, b2 is decided to be “0”. In FIG. 2, b2 is “1”.
Subsequently, the bit values of the third and subsequent bits are decided sequentially so that Vref becomes closer to Vin and when the bit value of the nth bit (the eighth bit) is decided, a state is brought about where Vref is closest to Vin, and therefore, the digital signal is output as an AD-converted value. When a voltage width corresponding to the least significant bit LSB of the AD-converted value to be decided is denoted by LSB, a difference of the AD-converted value to be decided to be Vin is within ±LSB/2. In the following explanation, in some cases, the voltage width corresponding to the least significant bit is denoted by LSB.
The algorithm to change the width, by which the above-mentioned reference analog signal Vref is changed, so that Vref becomes closer to Vin while reducing the width changed in the previous step to ½ is referred to as a binary conversion algorithm.
In recent years, an increase in operation speed is demanded also for the sequential comparison-type ADC. In the case of the sequential comparison-type ADC in FIG. 1, there is a possibility that determination will be erroneous unless the comparison by the comparator 12 is performed after the reference analog signal Vref output by the DA converter 14 has been sufficiently settled, and if the determination of the comparator 12 is erroneous once, it cannot be corrected and a large conversion error will result. Because of this, it is necessary to lengthen the time of each step so that the reference analog signal Vref output by the DA converter 14 is settled sufficiently in order to maintain precision, and therefore, it is difficult to increase the speed.
In order to meet the demand of both maintenance of precision and increase in speed, the applicants of the present application and the inventors of the invention of the present application have disclosed a sequential comparison-type ADC comprising three comparators in U.S. Pat. No. 7,561,094 B2.
FIG. 3 is a block diagram showing the configuration of the sequential comparison-type ADC comprising three comparators described in U.S. Pat. No. 7,561,094 B2. FIG. 4 is a diagram explaining the conversion operation in the sequential comparison-type ADC in FIG. 3.
As shown in FIG. 3, the sequential comparison-type ADC described in U.S. Pat. No. 7,561,094 B2 comprises three comparators 12H, 12M, and 12L, a sequential comparison control circuit 13A, and a DA converter (digital-to-analog converter) 14A. The input analog signal SA is held temporarily in the sample-holding circuit 11 and input to the comparator 12 as the input signal Vin. The DA converter 14A outputs three different reference analog signals Vh, Vm, and Vl. The three comparators 12H, 12M, and 12L compare the input signal Vin with the reference analog signals Vh, Vm, and Vl, respectively. The comparison results are input to the sequential comparison control circuit 13A.
As shown in FIG. 4, it is assumed that the sequential comparison-type ADC in FIG. 3 has an n-bit (here, 8-bit) resolution and the full-scale voltage is VFS. In the first step, the sequential comparison control circuit 13A outputs a digital signal whose bit value of the first bit (b1) is “1” and whose bit values of the second and subsequent bits (b2 to bn) are “0”. The DA converter 14A generates and outputs the reference analog signal Vm corresponding to the digital signal, the reference analog signal Vh of a voltage higher than Vm, and the reference analog signal Vl of a voltage lower than Vm. The difference between Vh and Vm and the difference between Vh and Vl correspond to the weight of the second bit, here, VFS/4, Vh=3VFS/4, and Vl=VFS/4.
The comparators 12H, 12M, and 12L compare the input signal Vin with the three reference analog signals Vh, Vm, and Vl, respectively, and outputs comparison results to the sequential comparison control circuit 13A. The sequential comparison control circuit 13A decides the bit values of the first bit (b1) and the second bit (b2) based on the three comparison results. For example, when Vin is larger than Vm and smaller than Vh, b1 is decided to be “1” and b2 “0”.
In the second step, the sequential comparison control circuit 13A outputs a digital signal whose b1 and b2 are the values (here, “1” and “0”) decided in the first step, whose bit value of the third bit (b3) is “1”, and whose bit values of the fourth and subsequent bits (b4 to bn) are “0”. The DA converter 14A generates and outputs the reference analog signal Vm=5VFS/8 corresponding to the digital signal, Vh=3VFS/4, and Vl=VFS/2. The comparators 12H, 12M, and 12L compare the input signal Vin with the three reference analog signals Vh, Vm, and Vl, respectively, and outputs comparison results to the sequential comparison control circuit 13A. The sequential comparison control circuit 13A decides the bit value of the third bit (b3) based on the three comparison results. For example, when Vin is smaller than Vm and larger than Vl, b3 is decided to be “0”.
Subsequently, the bit values of the fourth and subsequent bits are decoded sequentially so that Vh, Vm, and Vl become closer to Vin while narrowing the difference between Vh and Vm and the difference between Vm and Vl and when the bit value of the nth bit (here, the eighth bit) is decided, an AD-converted value closest to Vin is decided. As described above, in the first step, the bit values of the first bit (b1) and the second bit (b2) are decided, and therefore, the total number of steps is seven.
As described above, in the sequential comparison-type ADC in FIG. 3, after the bits up to the pth bit are decided and when the (p+1)th bit is decided, Vm(p+1)=Vj(p)+V(p+1) is set. Here, Vj(p) is a DA-converted output for the decided bit number p from the higher bits and V(p+1) is a DA-converted output having a weight of the (p+1)th bit from the higher bits. Vh is Vm to which the weight of the (p+1)th bit is added and Vh(p+1)=Vm(p+1)+V(p+1) holds. Vl is Vm from which the weight of the (p+1)th bit is subtracted and Vh(p+1)=Vm(p+1)−V(p+1) holds. Comparison of the input signal with the three reference analog signals Vh, Vm, and Vl is performed. When the input signal Vin is determined to be between Vh, Vm, and Vl, the above-described procedure is repeated with p being replaced with p+1.
In the second and subsequent steps, if normal, the input signal Vin should be between Vh and Vm or between Vm and Vl. However, when noise overlaps the input signal Vin or the settlement of the DA converter is insufficient, it may happen that the input signal Vin is determined to be equal to or higher than Vh or equal to or lower than Vl. When the input signal Vin is determined to be equal to or higher than Vh, the sequential comparison control circuit 13A corrects the decided bit values so that Vh(p) is Vj(p) and generates a digital value so that the DA-converted value corresponding to Vh(p)(=Vj(p)) to which the DA-converted value of V(p+1) is added is Vm(p+1) and outputs the digital value to the DA converter 14. That is, Vm(p+1)=Vj(p)+V(p+1) holds. Similarly, when the input signal Vin is determined to be equal to or lower than Vl, the sequential comparison control circuit 13A corrects the decided bit values so that Vl(p) is Vj(p) and generates a digital value so that the DA-converted value corresponding to Vl(p)(=Vj(p)) from which the DA-converted value of V(p+1) is subtracted is Vm(p+1) and outputs the digital value to the DA converter 14. That is, Vh(p+1)=Vm(p+1)−V(p+1) holds. In this manner, it is possible to correct the value of the higher bit once decided in a subsequent step, and therefore, even in the state where noise overlaps the input signal Vin or when an error occurs by performing AD conversion in the state where the settlement of the DA converter is insufficient, it is possible to correct the error later.
FIG. 5 is a diagram explaining error correction in the sequential comparison-type ADC. What is a problem is a relationship between the input signal Vin and the reference analog signals Vh, Vm, and Vl and the case where the reference analog signals Vh, Vm, and Vl change is also a problem. For the sake of simplification of explanation, an example is explained, in which the three reference analog signals Vh, Vm, Vl output from the DA converter 14A are correct and the voltage of the input signal Vin is not settled during the first three steps but increases gradually.
As shown in FIG. 5, in the first step, the input signal Vin is increasing and determined to be between Vm(=VFS/2) and Vl(=VFS/4). The sequential comparison control circuit 13A decides b1=0 and b2=1 based on the comparison result and as a digital value in the second step, outputs a digital signal whose b1=0, b2=1, b3=1, and b4 to bn=0. The DA converter 14 generates and outputs the reference analog signal Vm=3VFS/8 corresponding to the digital signal, Vh=VFS/2, and Vl=VFS/4. In the second step, the input signal Vin further increases and Vin is determined to be larger than Vh(=VFS/2). The comparison result does not agree with the decided b1=0 and b2=1, and therefore, the sequential comparison control circuit 13A corrects them to b1=1 and b2=0 and further decides b3=0 and as a digital value in the second step, outputs a digital signal whose b1=1, b2=0, b3=0, b4=1, and b5 to bn=0. The DA converter 14A generates and outputs the reference analog signal Vm=9VFS/16 corresponding to the digital signal, Vh=5VFS/8, and Vl=VFS/2. In the third step, the input signal Vin ceases increasing and is settled and determined to be between Vh(=5VFS/8) and Vm(=9VFS/16). This comparison result agrees with the decided bit values, and therefore, b4=1 is decided. Similarly as above, the bits up to b8 are decided.
The sequential comparison-type analog-to-digital converter comprising three comparators described in U.S. Pat. No. 7,561,094 B2 is explained as above. However, the number of comparators is not limited to three and two or four or more comparators may be comprised and depending on the number of comparators, the magnitude of an error that can be corrected in each step differs.
In the sequential comparison-type ADC described in U.S. Pat. No. 7,561,094 B2 explained above, a set value of the DA converter in a certain comparison step is regarded as the reference analog signal Vm at the center and to this or from this, a weight of a bit to be determined in the next step is added or subtracted and thus the reference analog signals Vh and Vl are set. It is possible to know whether an error occurs in the determination depending on which range the input signal is located with respect to the three reference analog signals. When the input signal is out of the range of Vh and Vl, it is determined that the determination in the previous step is erroneous and the higher bits decided before the step are corrected and Vh, Vm, and Vl are also corrected in accordance with the correct range. Subsequently, by repeating this processing sequentially to the least significant bit, it is possible to make a determination with sufficient redundancy for the higher bits and it is also made possible to correct the erroneous conversion. The redundancy of a sequential comparison-type ADC is described in, for example, “SAR ADC Algorithms with Redundancy” by Tomohiko OGAWA, Haruo KOBAYASHI, Yosuke TAKAHASHI, and Masao HOTTA, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, Circuit and System Research Group, Tokyo (October 2007).